CE Advisory Board

The Computer Engineering Program is extremely fortunate to have an advisory board of highly-respected leaders in our field who volunteer their time and lend us their vision on research, education, and diversity as they relate to our growing program.

The board was formed in 2008 and meets annually. Members come from a variety of academic and industrial backgrounds and all have particular insight into building world-class computer engineering organizations.

photo of Bill Eklow

Bill Eklow, Distinguished Manufacturing Engineer, Cisco Systems, Inc.


Bill Eklow is a Distinguished Manufacturing Engineer at Cisco Systems, Inc. In his role, Bill works with design engineers, component suppliers, board and system integrators and test engineers to identify and implement processes and tools that will improve the “end-to-end” (supplier to customer) quality of Cisco’s products. Bill has been working at Cisco for over 19 years. Prior to joining Cisco, Bill worked at Tandem Computers for 12 years as a Senior Test Engineer/Test Architect. Before Tandem, Bill worked as a test engineer at Fairchild (when it was still Fairchild).


Bill has been involved in the test industry for over 36 years and has been involved with IEEE for more than 20 years. Bill is a fellow of the IEEE, a Golden Core member and an Eta Kappa Nu member. Bill was the chair of the 1149.6-2002 working group and chair of the current IEEE 1149.6 revision (2015). Bill has also been an active working group member in the IEEE 1149.1, P1687 and P1838 working groups. Bill has been Program and General Chair for IEEE International Test Conference . Bill is also the general chair for the IEEE Board Test Workshop and is chair of the IEEE Board Test Technical Activities Committee (BTTAC). Bill is also a Technical Working Group Chair for the International Technology Roadmap for Semiconductors (ITRS).


Bill has funded several research projects and as a result has authored and co-authored several papers. He has also contributed to two books. Bill has been an advisory board member for the University of Washington at Tacoma, and California State University at Chico.


Among Bill’s hobbies are: golf, dining at 3 star restaurants, visiting Starbucks coffee shops and collecting Hard Rock Café tee shirts from all over the world.

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Mark McDermott, Director of Research Collaborations and Entrepreneur in Residence, ARM


Mark McDermott has 40 years of experience in product development of silicon systems. He is currently Director of Research Collaborations and Entrepreneur in Residence at ARM. Additionally he is an Adjunct Faculty member in the Electrical and Computer Engineering Department at the University of Texas at Austin where he teaches graduate level courses in silicon system design and technical entrepreneurship.


Mark received a Bachelors degree in Electrical Engineering from the University of New Mexico, a Masters and Ph.D. in Electrical Engineering from the University of Texas at Austin.  Mark is a registered professional engineer and a member of the IEEE, ACM and TSPE. He has 19 patents and a number of publications in the areas of IC design and engineering management.


Prior industrial experience include: Senior Director at Apple, Inc., VP & GM at Intrinsity, Inc., VP of Engineering at Coherent Logix, CEO of DynaFlow Computing, Inc., VP Engineering at Somerset Embedded Technologies, Inc., VP Engineering at VisionFlow, Inc., General Manager and Director of the Texas Development Center for Intel Corporation, Director of the PowerPC Somerset Design Center and Director of the Austin Design Center for Cyrix, Inc. Mark co-founded DynaFlow Computing, The Learning Labs, Somerset Embedded Technologies, Inc., VisionFlow, Inc., Logical Silicon Solutions, Inc., Accelerated Solutions Corp., and MonoCom Systems, Inc.

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Margaret Martonosi (Advisory Board Chair), Professor, Princeton University


Margaret Martonosi is the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She also holds an affiliated faculty appointment in Princeton EE. From 2005-2007, she served as Associate Dean for Academic Affairs for the Princeton University School of Engineering and Applied Science. In 2011, she served as Acting Director of Princeton's Center for Information Technology Policy (CITP).

Martonosi's research interests are in computer architecture and mobile computing, with particular focus on power-efficient systems. Her work has included the development of the Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on hardware-software interface approaches to manage heterogeneous parallelism and power-performance tradeoffs in systems ranging from smartphones to chip multiprocessors to large-scale data centers.

Martonosi is a Fellow of both IEEE and ACM. She was the 2013 recipient of the Anita Borg Institute Technical Leadership Award. She has also received the 2013 NCWIT Undergraduate Research Mentoring Award and the 2010 Princeton University Graduate Mentoring Award. In addition to many archival publications, Martonosi is an inventor on six granted US patents, and has co-authored a technical reference book on power-aware computer architecture. She serves on the Board of Directors of the Computing Research Association (CRA). Martonosi completed her Ph.D. at Stanford University, and also holds a Master's degree from Stanford and a bachelor's degree from Cornell University, all in Electrical Engineering.

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Joel S. Emer, Senior Distinguished Research Scientist, Architecture Research Group, NVIDIA


Dr. Joel S. Emer joined NVIDIA in 2014 and is a member of the Architecture Research group. He is also a Professor of the Practice at MIT. He is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research.  Previously he worked at Compaq and Digital Equipment Corporation.


Emer has held various research and advanced development positions investigating processor microarchitecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. More recently, he has been recognized for his contributions in the advancement of simultaneous multithreading technology, processor reliability analysis, cache organization and spatial architectures.


Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer has received numerous public recognitions, including being named a Fellow of both the ACM and IEEE, and he was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.

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Ryan Kastner, Professor, University of California, San Diego


Ryan Kastner is a professor in the Department of Computer Science and Engineering at the University of California, San Diego.. He received a PhD in Computer Science (2002) at UCLA,, a Masters degree in engineering (2000) and Bachelor degrees (BS) in both Electrical Engineering and Computer Engineering (1999), all from Northwestern University. He spent the first five years after his PhD as a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara.

Professor Kastner’s current research interests fall into three areas: hardware acceleration, hardware security, and remote sensing. He is the co-director of the Wireless Embedded Systems Master of Advanced Studies Program. He also co-directs the Engineers for Exploration Program. He has published over 150 technical articles, and has authored three books, “Synthesis Techniques and Optimizations for Reconfigurable Systems”, “Arithmetic Optimizations for Polynomial Expressions and Linear Systems”, and “Handbook on FPGA Design Security”. He has served as member of numerous conference technical committees spanning topics like reconfigurable computing (ISFPGA, FPL, FPT), hardware design (DAC, ICCAD, DATE), hardware security (HOST), and underwater networking (WUWNet).

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Gee Rittenhouse, Senior VP / General Manager Cloud and Virtualization Group, Cisco Systems


Gee Rittenhouse is Vice President and General Manager of Cisco’s Cloud and Virtualization Group (CVG), a market-driven organization leading industry transformation in cloud infrastructure software and services. 

Before joining Cisco, Gee helped launch Alcatel-Lucent's Software, Services, and Solutions business and led that business to profitability as Chief Operating Officer. Prior to that, he led Bell Labs through the most extensive transformation in its recent history with the merger of Bell Labs and Alcatel's Research group. He retired as President of Bell Labs.  Pioneering an open innovation model, Rittenhouse also helped create the world's most ambitious research collaboration effort on green networks called GreenTouch, a consortium with approximately 60 leading industrial and academic research groups from around the world.

Rittenhouse is a highly respected IT industry leader with over 20 years of leadership experience in the telecommunications industry. He has appeared before the U.S. Congress, U.S. FCC, European Presidential Commission, and World Economic Forum, and has given a TED talk. He has been elected two times to the Global Telecoms Business Power 100, has published numerous articles and holds over a dozen patents.

He is currently a member of the Advisory Board for the University of California, Santa Barbara CE Department and has served as Chairman of the Board of Greentouch and as an ALU Foundation Board member with the goal of educating disadvantaged women world-wide.


Rittenhouse has a PhD in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology, is a Senior Member of IEEE, and a past winner of the IEEE Communication Quality and Reliability (CQR) Chairman’s Award.

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Vivek Sarkar, Professor and Chair of Computer Science, Rice University


Vivek Sarkar is Professor and Chair of Computer Science at Rice University.  He conducts research in multiple aspects of parallel software including programming languages, program analysis, compiler optimizations and runtimes for parallel and high performance computer systems. He currently leads the Habanero Extreme Scale Software Research project at Rice University, and serves as Associate Director of the NSF Expeditions Center for Domain-Specific Computing.  Prior to joining Rice in July 2007, Vivek was Senior Manager of Programming Technologies at IBM Research.  His responsibilities at IBM included leading IBM’s research efforts in programming model, tools, and productivity in the PERCS project during 2002- 2007 as part of the DARPA High Productivity Computing System program.  His prior research projects include the X10 programming language, the Jikes Research Virtual Machine for the Java language, the ASTI optimizer used in IBM’s XL Fortran product compilers, the PTRAN automatic parallelization system, and profile-directed partitioning and scheduling of Sisal programs.  In 1997, he was on sabbatical as a visiting associate professor at MIT, where he was a founding member of the MIT Raw multicore project. 


Vivek became a member of the IBM Academy of Technology in 1995, the E.D. Butcher Chair in Engineering at Rice University in 2007, and was inducted as an ACM Fellow in 2008.  He holds a B.Tech. degree from the Indian Institute of Technology, Kanpur, an M.S. degree from University of Wisconsin-Madison, and a Ph.D. from Stanford University.  Vivek has been serving as a member of the US Department of Energy’s Advanced Scientific Computing Advisory Committee (ASCAC) since 2009.

Past Advisory Board Members

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John R. White, Executive Director & Chief Executive Officer, ACM — Association for Computing Machinery (CEAB Member — 2008-2014)


Dr. John R. White has served as ACM Executive Director and Chief Executive Office since January 1999. As CEO Dr. White is responsible for working with ACM senior leadership (the officers, the board of directors, and over 1,000 volunteers) in setting and delivering ACM’s strategic direction. During John’s tenure, ACM membership has grown to an all-time high, its scholarly publishing program has doubled in size, and the Association is increasingly involved in issues related to the image and health of the computing discipline and field worldwide.


Prior to joining ACM, John was Manager of the Computer Science Laboratory at the Xerox Palo Alto Research Center (PARC). White spent seventeen years at Xerox PARC leading several research groups, including the PARC group that developed and delivered DocuPrint, Xerox’ series of high-end, high-speed networked printing products. As head of the Computer Science Lab, he managed research teams exploring future offerings in networked electronic document systems, services, and commerce. Prior to his tenure at Xerox PARC, White was a Professor of Computer Science at the University of Connecticut.


Dr. White has been a long-time advocate of the ACM, serving as its President from 1990-92, as well as assuming many key ACM volunteer roles over the past two decades.


Dr. White received his Ph.D. in computer science, M.S. in computer science, and B.A. in mathematics, all from the University of California, Santa Barbara. He has a number of refereed publications and holds a US patent. He is a Fellow of the ACM, a recipient of the ACM Outstanding Contribution award, as well as a Xerox PARC Excellence in Science and Technology Award. Dr. White has served on the boards of the Computing Research Association, Computing Sciences Accreditation Board, and the Publishers International Linking Association (CrossRef).

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David E. Culler, Professor, University of California, Berkeley (CEAB Chair — 2008-2012)


David E. Culler received his B.A. from UC Berkeley, 1980, and a M.S. and Ph.D. from MIT, 1985 and 1989 respectively. He joined the EECS faculty in 1989 and is the founding Director of Intel Research, UC Berkeley. He is a member of the National Academy of Engineering, an ACM Fellow, and was selected in Scientific American Top 50 Researchers and Technology Review 10 Technologies that Will Change the World. He was awarded the NSF Presidential Young Investigator and the Presidential Faculty Fellowship. His research addresses networks of small, embedded wireless devices, planetary-scale internet services, parallel computer architecture, parallel programming languages, and high performance communication. This includes TinyOS, Berkeley Motes, PlanetLab, Networks of Workstations (NOW), Internet services, Active Messages, Split-C, and the Threaded Abstract Machine (TAM).

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Norman P. Jouppi, HP Fellow and Director, Exascale Computing Lab, HP Labs (CEAB Member — 2008-2011)


Norman P. Jouppi is known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area, and power. He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence. His recent work includes implications of emerging nanophotonic technology on computer systems.


Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980. While at Stanford, he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification. Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a Staff Fellow at Compaq’s Western Research Laboratory. From 1984 through 1996 he was a consulting assistant/associate professor in the department of electrical engineering at Stanford University.


He currently serves as past chair of ACM Special Interest Group on Computer Architecture (SIGARCH) and is on the Computing Research Association (CRA) board. He is on the editorial board of Communications of the ACM and IEEE Computer Architecture Letters, and is a Fellow of the ACM and the IEEE. He holds more than 35 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.