Friday, March 2 at 10:00am

Electrical & Computer Engineering Conference Room (HFH 4164)

Electrical & Computer Engineering and CE Program Present:

John Sartori, Ph.D. Candidate in ECE at the University of Illinois at the Urbana-Champaign

"Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications"

Abstract

All of computing today relies on an abstraction where software expects hardware to behave flawlessly for all inputs, under all conditions. While this abstraction worked well historically, due to the relatively small magnitude of variations in hardware and environment, computing will increasingly be done with devices and circuits that are inherently stochastic because of how small they are, or whose behavior is stochastic due to manufacturing and environmental uncertainties. For such emerging circuits and devices, the cost of guaranteeing correctness will be prohibitive, and we will need to fundamentally rethink the correctness contract between hardware and software. Such rethinking becomes particularly compelling considering that a significant amount of energy is wasted in guaranteeing reliability even for applications that are inherently error tolerant.

The primary goal of my research has been to revisit the correctness contract between hardware and software to enable extremely energy-efficient computing. Instead of computing machines where hardware variations are always hidden from the software behind conservative design specifications, my research advocates computing machines (stochastic processors) where (a) these variations are opportunistically exposed to the highest layers of software in the form of hardware errors, and (b) software and hardware are optimized to maximize energy savings while delivering acceptable outputs, in spite of errors. In this talk, I will describe architecture and physical design-based approaches to build and optimize stochastic processors. I will also discuss our ongoing work on building applications for such processors. As a proof of concept, I will discuss an example prototype system based on commodity hardware that exploits application-level error tolerance to maximize system efficiency. Finally, I will outline some other promising approaches to energy-efficient computing for emerging applications.

Biography

John Sartori received a B.S. degree in electrical engineering, computer science, and mathematics from the University of North Dakota, Grand Forks and a M.S. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC). He is currently finishing a Ph.D. in electrical and computer engineering at UIUC. His research interests include stochastic computing, energy-efficient computing, and system architectures for emerging workloads. John's research has been recognized by a best paper award [CASES 2011] and a best paper award nomination [HPCA 2012] and has been the subject of several keynote talks and invited plenary lectures. His work has been chosen to be the cover feature for popular media sources such as BBC News and HPCWire, and has also been covered extensively by scientific press outlets such as the IEEE Spectrum and the Engineering and Technology Magazine. When not doing research, John enjoys outdoor activities in the balmy Champaign weather, playing music, and studying and discussing philosophy.

Monday, October 31 at 3:30p

Computer Science Conference Room (HFH 1132)

Computer Science Department and CE Program Present:

David A. Wood, Professor, Computer Science at the University of Wisconsin, Madison

"Two Scalable Core Architectures for Power-Constrained CMPs"

Abstract

Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased core-per-socket count will continue, despite a lack of parallel software. Future CMPs must deliver thread-level parallelism when software provides threads to run, but must also continue to deliver high single-thread performance--via instruction-level and memory-level parallelism--to mitigate sequential bottlenecks and/or to guarantee service-level agreements. However, power limitations will prevent conventional cores from exploiting both simultaneously.

The Wisconsin Multifacet project has recently developed two alternative scaleable core architectures, which can scale their execution logic up to run single threads fast, or down to run multiple threads within a fixed power budget. WiDGET (Wisconsin Decoupled Grid Execution Tiles) decouples thread context management from a sea of simple execution units. WiDGET’s decoupled design provides flexibility to alter resource allocation for a particular power-performance target while turning off unallocated resources. Forwardflow dynamically builds an explicit internal dataflow representation from a conventional instruction set architecture, using forward dependence pointers to guide instruction wakeup, selection, and issue. Forwardflow’s backend is organized into discrete units that can be individually (de-)activated, allowing each core’s performance to be scaled by system software at the architectural level.

Biography

Professor David A. Wood is a Professor in the Computer Sciences Department at the University of Wisconsin, Madison and has a joint appointment in Electrical and Computer Engineering.

Dr. Wood was named an ACM Fellow (2005) and IEEE Fellow (2004), received the University of Wisconsin's H.I. Romnes Faculty Fellowship (1999), received the National Science Foundation's Presidential Young Investigator award (1991), and earned his Ph.D. in Computer Sciences from the University of California, Berkeley (1990). Dr. Wood is Chair of ACM Special Interest Group on Computer Architecture (SIGARCH), Area Editor (Computer Systems) of ACM Transactions on Modeling and Computer Simulation, is Associate Editor of ACM Transactions on Architecture and Compiler Optimization, served as Program Committee Chairman of ASPLOS-X (2002), and has served on numerous program committees. Dr. Wood is an ACM Fellow, an IEEE Fellow, and a member of the IEEE Computer Society. Dr. Wood has published over 70 technical papers and is an inventor on twelve U.S. and International patents.

Dr. Wood co-leads the Wisconsin Multifacet Project with Prof. Mark Hill which is exploring techniques for improving the availability, designability, programmability, and performance of commercial multiprocessor and chip multiprocessor servers.

Wednesday, November 2 at 3:30

Computer Science Conference Room (HFH 1132)

Computer Science Department and CE Program Present:

John D. Kubiatowicz, Professor, EECS at UC, Berkeley

"Optimizing the Layout and Error Properties of Quantum Circuits"

Abstract

In this talk, I will discuss Berkeley's efforts at designing efficient architectures for Ion-trap quantum computers and will present our Computer Aided Design (CAD) flow for quantum circuits. The CAD flow can automatically insert quantum error correction, partition and layout quantum circuits, optimize the placement of teleportation and error correction operations, and evaluate the error properties of the resulting layout. With the CAD tool, we are able to study and optimize large quantum circuits (such as adders, Shor's factoring, etc). Among other things, I will argue that quantum circuits should be evaluated in the context of suitable metrics such as ADCR -- the probabilistic equivalent of the Area-Delay product. This talk will reinforce some of the important recent lessons in quantum computing, such as the fact that communication cost and errors significantly impact the behavior of quantum circuits -- so much so that a full layout of a target quantum circuit is desirable. Among other things, I will (1) present Qalypso, a quantum datapath architecture that optimizes ancilla generation, (2) discuss the design of routeable teleportation networks, (3) show how a simple error-correction optimization based circuit retiming can improve ADCR by an order of magnitude or more. This later optimization can produce circuits of greater reliability by removing error correction steps.

Biography

John Kubiatowicz is a Professor of EECS at the University of California at Berkeley. Prof. Kubiatowicz received a dual B.S in Physics and Electrical Engineering (1987), as well as an MS in EECS (1993) and PhD in EECS (1998), all from MIT. Kubiatowicz was chosen as one of Scientific American's top 50 researchers in 2002, one of US News and World Report's "people to watch for 2004", and is the recipient of an NSF PCASE award (2000). Kubiatowicz's research interests include quantum computing design tools and architectures, manycore Operating Systems architecture and resource management, multiprocessor and manycore CPU designs, Internet-scale distributed systems, and long-term digital information preservation.