2009-10 CE Seminar Series headerlink to the CE website home page

photo of Joel Emer

HP Labs and the CE Program Present:

Joel S. Emer, Architecture Group Director
Microarchitecture Research, Intel Corporation

 

"An Evolution of General Purpose Processing: Reconfigurable Logic Computing"


The historical improvements in the performance of general-purpose processors have long provided opportunities for application innovation. Word processing, spreadsheets, desktop publishing, networking and various game genres are just some of the many applications that have arisen because of the increasing capabilities and the versatility of general-purpose processors. Key to these innovations is the fact that general-purpose processors do not predefine the applications that they are going to run.

 

At the far extreme of non-generality is dedicated logic, which when applied to a specific task will invariably out perform and out power/perform a general-purpose processor. However, the time, difficulty and cost of special purpose design preclude dedicated logic from serving as a viable avenue for application innovation.

Recently, a middle ground between fully general-purpose computing and dedicated logic has bee showing increasing promise. In specific, reconfigurable logic, typically in the form of FPGAs, addresses many of the cost-related liabilities of dedicated logic and is increasingly being applied to general computation problems.

 

In this talk, we will examine the possibilities for reconfigurable logic as a foundation for general-purpose computation. We will look at its potential and attempt to provide an analogy between the state of reconfigurable logic computing today and the early days of conventional computing. In that light, we consider how reconfigurable logic might recapitulate the history of general-purpose computation by looking at how it can fit into the architectural framework that we have generally reserved for conventional processors, how it can be more seamlessly be incorporated into a system and how reconfigurable logic might be made more efficient and be more effectively programmed by looking at the semantic gap between programming languages and the compute fabric itself.


Biography

Joel Emer is an Intel Fellow and Director of Microarchitecture Research at Intel in Hudson, Massachusetts. Previously he worked at Compaq and Digital Equipment Corporation where he has held various research and advanced development positions investigating processor microarchitecture for a variety of VAX and Alpha processors and developing performance modeling and evaluation techniques. His research included pioneering efforts in simultaneous multithreading, analysis of the architectural impact of soft errors and early contributions to the now pervasive quantitative approach to processor evaluation. His current research interests include memory hierarchy design, processor reliability, reconfigurable logic-based computation and performance modeling. In his spare time, he serves as visiting faculty at MIT.

 

Emer received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 — both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer holds over 25 patents and has published more than 35 papers. He is a Fellow of both the ACM and the IEEE, and was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.

photo Geoffrey M. Voelker

HP Labs and the CE Program Present:

Geoffrey M. Voelker, Professor, UC San Diego

 

"Spam Analytics: Exploring the Technical and Economic Factors in Bulk Email Scams"


Today, the large-scale compromise of Internet hosts serves as a platform for supporting a range of criminal activity in the so-called Internet underground economy. By far the best known example of this activity is unsolicited bulk email (spam), which has become the de facto delivery mechanism for a range of criminal endeavors, including phishing, securities manipulation, identity theft, and malware distribution.

 

The "conversion rate" of spam — the probability that an unsolicited email will ultimately elicit a "sale" — underlies the entire spam value proposition. However, our understanding of this critical behavior is quite limited, and the literature lacks any quantitative study concerning its true value. In this talk I will present a methodology for measuring the conversion rate of spam. Using a parasitic infiltration of an existing botnet's infrastructure, we analyze two spam campaigns: one designed to propagate a malware Trojan, the other marketing on-line pharmaceuticals. For over 240 million spam e-mails we identify the number that are successfully delivered, the number that pass through popular anti-spam filters, the number that elicit user visits to the advertised site, and the number of "sales" produced.

 

This work is in collaboration with Brandon Enright, Chris Kanich, Christian Kreibich (ICSI), Kirill Levchenko, Vern Paxson (ICSI/Berkeley), and Stefan Savage. It is part of a larger effort within the Collaborative Center for Internet Epidemiology and Defenses (CCIED), a joint NSF Cybertrust Center with UCSD and ICSI (http://www.ccied.org).

 

Biography

Geoffrey M. Voelker is a Professor at the University of California at San Diego. His research interests include operating systems, distributed systems, and computer networks. He received a B.S. degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1992, and the M.S. and Ph.D. degrees in Computer Science and Engineering from the University of Washington in 1995 and 2000, respectively.

photo Randy H. Katz

The Institute for Energy Efficiency, HP Labs and CE Program Present:

 

Randy H. Katz, UC Berkeley, United Microelectronics Corporation Distinguished Professor

 

"A Computer Scientist Looks at the Energy Problem"


In this talk, we describe LoCal, a research project at Berkeley that applies the lessons of the Internet, for building distributed and robust communications infrastructures, to a radical new architecture for energy generation, distribution and sharing. We introduce the concept of packetized energy, stored and forwarded to where it is locally needed, exploiting technology for more efficient energy storage. Like the Internet, quality is achieved end-to-end via protocols over a best-effort, resilient and scalable infrastructure. Distributed management and storage enables dramatic reductions in peak-to-average energy consumption, influencing infrastructure provisioning and investment, and enabling a virtuous cycle of power-limited design. Our architectural building block, intelligent power switching, permits use of diverse, even non-traditional energy storage. Rather than replacing the grid, we overlay it, providing independence from existing generation and transmission systems. Our approach is suited to environments where it is desirable to add incremental generation and distribution, where a centralized infrastructure is prohibitively expensive to deploy as in third world or remote regions (e.g., military or humanitarian operations), or where continued operation in the face of natural disasters is highly desirable (e.g., post-Katrina or post-earthquake disruption of the wide-area energy grid). Management of local demand is also important to dynamically reduce load to remain independent of the grid for as long as possible.

 

Biography:

Randy Howard Katz received his undergraduate degree from Cornell University, and his M.S. and Ph.D. degrees from the University of California, Berkeley. He joined the Berkeley faculty in 1983, where since 1996 he has been the United Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science. He is a Fellow of the ACM and the IEEE, and a member of the National Academy of Engineering and the American Academy of Arts and Sciences. In 2007, he received an honorary doctorate from the University of Helsinki. He has published over 250 refereed technical papers, book chapters, and books. His textbook, Contemporary Logic Design, has sold over 100,000 copies in two editions, and has been used at over 200 colleges and universities. He has supervised 49 M.S. theses and 39 Ph.D. dissertations (including one ACM Dissertation Award winner and ten women). His recognitions include thirteen best paper awards (including one "test of time" paper award and one selected for a 50 year retrospective on IEEE Communications publications), three best presentation awards, the Outstanding Alumni Award of the Computer Science Division, the CRA Outstanding Service Award, the Berkeley Distinguished Teaching Award, the CS Division's Diane S. McEntyre Award for Excellence in Teaching, the Air Force Exceptional Civilian Service Decoration, the IEEE Reynolds Johnson Information Storage Award, the ASEE Frederic E. Terman Award, the IEEE James H. Mulligan Jr. Education Medal, the ACM Karl V. Karlstrom Outstanding Educator Award, and the ACM Sigmobile Outstanding Contributor Award.


In the late 1980s, with colleagues at Berkeley, he developed Redundant Arrays of Inexpensive Disks (RAID), a $15 billion per year industry sector. While on leave for government service in 1993-1994, he established whitehouse.gov and connected the White House to the Internet. His BARWAN Project of the mid-1990s introduced vertical handoffs and efficient transport protocols for mobile wireless networks. His current research interests are the architecture of Internet Datacenters, particularly frameworks for datacenter-scale instrumentation and resource management. With David Culler and Seth Sanders, he has started a new research project on Smart Energy Networks, called LoCal. Prior research interests have included: database management, VLSI CAD, high performance multiprocessor (Snoop cache coherency protocols) and storage (RAID) architectures, transport (Snoop TCP) and mobility protocols spanning heterogeneous wireless networks, and converged data and telephony network and service architectures.

photo Rajesh K. Gupta

HP Labs and the CE Program Present:

Rajesh K. Gupta, Professor, UC San Diego


"Collaborative Heterogeneity for Building Energy Efficient Systems"


Computing today operates in distributed, dynamic and sensor rich environments. Consequently, designing computer systems for low power entails not only the use of the best design practices in various components from processors, memories to radios but also awareness of power-related decision making across subsystems and functional abstractions. What then are the engineering principles that can be applied to guide system designer with low power consumption as a key design criterion? This talk is a retrospective look at the strategies deployed to reduce power consumption and improve energy efficiency across a number of efforts. Among the important lessons learnt is the need for algorithm/architecture co-design to support aggressive duty-cycling in systems. We explore the notion of “collaborative heterogeneity” in building integrated communication and computing systems that can enable us to reach achievable efficiencies while ensuring important performance and availability requirements.

 

Biography:

Rajesh K. Gupta is a professor of Computer Science and Engineering at UC San Diego, and holds the QUALCOMM endowed chair. His research interests are in energy efficient systems that have taken turn towards large-scale energy use in recent years. He directs smart buildings/smart grids task force at UC San Diego in his role as associate director for the California Institute for Telecommunications and Information Technology (CalIT2).

 

His recent contributions include SystemC modeling and SPARK parallelizing high-level synthesis, both of which are publicly available and have been incorporated into industrial practice. Earlier Gupta lead or co-lead DARPA-sponsored efforts under the Data Intensive Systems (DIS) and Power Aware Computing and Communications (PACC) programs that demonstrated architectural adaptation and compiler optimizations in building high performance and energy efficient system architectures.

 

Gupta's ongoing efforts include energy-efficient data-centers and large scale computing using memory-coherent algorithmic accelerators and non-volatile storage systems. In recent years, Gupta and his students have received a best paper award at IEEE/ACM DCOSS’08 and a best demonstration award at IEEE/ACM IPSN/SPOTS’05. Gupta received a BTech in EE from IIT Kanpur, MS in EECS from UC Berkeley and a PhD in Electrical Engineering from Stanford University. He currently serves as EIC of IEEE Embedded Systems Letters. Gupta is a Fellow of the IEEE.

photo of Norman Jouppi

The Institute for Energy Efficiency and CE Program Present:

Norman Jouppi, Director, Exascale Computing Lab - HP Labs


"System Implications of Integrated Photonics"


Micron-scale photonic devices integrated with standard CMOS processes have the potential to dramatically increase system bandwidths, performance, and configuration flexibility while reducing system power. Small devices have many advantages: reduced power, increased density, and increased speed. By integrating many thousands of these devices on a chip, photonics could potentially be used for most high-speed off-chip and global on-chip communication. Integrated photonics has many advantages at the board and rack scale as well. Recent high-speed board-level electrical signaling (>2.5GHz) precludes the use of multi-drop busses or communication over long distances on ordinary inexpensive PC board materials. By using photonics, high fan-out and high-fan-in bus structures can be built. Due to the low loss of optical signals versus distance, these structures can even be distributed over rack-scale distances. This dramatically increases system flexibility while reducing interconnect power.

 

As an example of the potential impact of photonics, I describe a system architecture for the 2017 time frame we call Corona. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We believe that in comparison with an electrically-connected many-core alternative, Corona could provide 2 to 6 times more performance on many memory intensive workloads, while simultaneously significantly reducing power.


Biography

Norman P. Jouppi is a Fellow and Director of the Exascale Computing Lab at HP Labs. He is known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area, and power. He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence. His recent work includes implications of emerging nanophotonic technology on computer systems.

 

Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980. While at Stanford, he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification. Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a Staff Fellow at Compaq’s Western Research Laboratory in Palo Alto, Calif. From 1984 through 1996 he was a consulting assistant/associate professor in the department of electrical engineering at Stanford University.

 

He currently serves as past chair of ACM Special Interest Group on Computer Architecture (SIGARCH), is on the ACM Council and on the Computing Research Association (CRA) board. He is on the editorial board of Communications of the ACM and IEEE Computer Architecture Letters, and is a Fellow of the ACM and the IEEE. He holds more than 35 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.

photo of Kim Hazelwood

The CE Program Presents:

Kim Hazelwood, Assistant Professor
Computer Science Department, University of Virginia

 

"A Case for Runtime Adaptation using Cross-Layer Approaches"

 

Modern computer system designers must consider many more factors than raw performance of individual applications. Thermal output, power consumption, reliability, heterogeneity, and dynamic resource contention have become first-order concerns. Yet many of these issues are transient in nature, are difficult to predict, and are expensive to completely avoid. These observations point toward the potential benefits of adaptive systems that detect and react to changing conditions as they arise.

 

An effective runtime adaptation framework can directly benefit from information gathered by various system layers. Unfortunately, research efforts in optimizing computer systems have historically targeted a single logical layer in the system stack, whether it has been optimization of the hardware (microarchitectures or circuits), the middleware (operating systems and virtual machines), or the software (static and dynamic compilation). A true adaptive system requires coordination of all layers to be effective, athese cross-layer solutions leverage the strengths of each layer. While hardware is ideal for detecting thermal emergencies, for instance, the middleware has a global view of the runtime environment, including resource contention and observed process heterogeneity, and the software has a global view of the opportunities for permanent code-based solutions that leverage dynamic information.

 

In this talk, I will make a case for dynamic adaptation as a solution for several modern architectural and system challenges, such as voltage noise, heterogeneity, and resource contention. I will discuss our research efforts in integrating the strengths of each design layer to provide cohesive, symbiotic solutions to these challenges. At the core of this work is the Pin dynamic instrumentation system, which we use to collate information gathered from the various system layers and to perform run-time code transformations. I will therefore discuss the myriad of implementation challenges we encountered when developing, optimizing, and supporting Pin. Finally, I will highlight the numerous benefits of runtime adaptation moving forward.


Biography

Kim Hazelwood is an Assistant Professor of Computer Science at the University of Virginia. She works at the boundary between hardware and software, with research efforts focusing on computer architecture, run-time optimizations, and the implementation and applications of virtual execution environments. She received the Ph.D. degree from Harvard University in 2004. Since then, she has become widely known for her active contributions to the Pin dynamic instrumentation system, which allows users to easily inject arbitrary code into existing program binaries at run time (www.pintool.org). Pin is widely used throughout industry and academia to investigate new approaches to program introspection, optimization, security, and architectural design. It has been downloaded over 40,000 times and cited in over 600 publications since it was released in July 2004.

 

Kim has published over 35 peer-reviewed articles related to computer architecture and virtualization. She has served on over a dozen program committees, including ISCA, PLDI, MICRO, and PACT, and is the program chair of CGO 2010. Kim is the recipient of numerous awards, including the FEST Distinguished Young Investigator Award for Excellence in Science and Technology, an NSF CAREER Award Woodrow Wilson Career Enhancement Fellowship, the Anita Borg Early Career Award, and research awards from Microsoft, Google, NSF, and the SRC. Her research has been featured in Computer World, ZDNet, EE Times, and Slashdot.

2009-2010 Seminars

Joel S. Emer, Architecture Group, Dir. Microarchitecture Research, Intel
"An Evolution of General Purpose Processing: Reconfigurable Logic Computing"

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Geoffrey M. Voelker, Professor, UCSD
"Spam Analytics: Exploring the Technical and Economic Factors in Bulk Email Scams
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Randy H. Katz, Professor, UC Berkeley
"A Computer Scientist Looks at the Energy Problem
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katz pptVideo and PowerPoint


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Rajesh K. Gupta, Professor, UCSD
"Collaborative Heterogeneity for Building Energy Efficient Systems
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Norman Jouppi, Director, Exascale Computing Lab - HP Lab
"System Implications of Integrated Photonics"

jouppi pptVideo / PowerPoint


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Kim Hazelwood, U. of Virginia
"A Case for Runtime Adaptation using Cross-Layer Approaches"