Monday, June 4 at 2:00pm

Computer Science Conference Room (HFH 1132)

HP Labs and CE Program Present:

Luis Ceze, Assistant Professor, Computer Science at the University of Washington

Biography

Luis Ceze, Assistant Professor, joined the Computer Science and Engineering faculty in 2007. His research focuses on computer architecture, programming languages and OS to improve the programmability, reliability and energy efficiency of computer systems, with emphasis on parallel and distributed systems. See the SAMPA research group.

He has co-authored over 50 papers in these areas and had several papers selected as IEEE Micro Top Picks and CACM research Highlights. He participated in the Blue Gene, Cyclops, and PERCS projects at IBM and is a recipient of several IBM awards. He is also a recipient of an NSF CAREER Award, a Sloan Research Fellowship and a Microsoft Research Faculty Fellowship. He co-founded Corensic, a UW CSE spin-off company.

He was born in São Paulo, Brazil. He received his Ph.D. in Computer Science from University of Illinois at Urbana-Champaign and his B.Eng. and M.Eng. in Electrical Engineering from University of São Paulo, Brazil.

Thursday, February 16 at 10:00am

Computer Science Conference Room (HFH 1132)

HP Labs and CE Program Present:

Daniel Sanchez, Ph.D. Candidate in EE, Stanford University

"Scaling Software and Hardware for Thousand-Core Systems"

Abstract

Scaling multicores to thousands of cores efficiently requires significant innovation across the software-hardware stack. On one hand, to expose ample parallelism, many applications will need to be divided in fine-grain tasks of a few thousand instructions each, and scheduled dynamically in a manner that addresses the three major difficulties of fine-grain parallelism: locality, load imbalance, and excessive overheads. On the other hand, hardware resources must scale efficiently, even as some of them are shared among thousands of threads. In particular, the memory hierarchy is hard to scale in several ways: conventional cache coherence techniques are prohibitively expensive beyond a few tens of cores, and caches cannot be easily shared among multiple threads or processes. Ideally, software should be able to configure these shared resources to provide good overall performance and quality of service (QoS) guarantees under all possible sharing scenarios.

In this talk, I will present several techniques to scale both software and hardware. First, I will describe a scheduler that uses high-level information from the programming model about parallelism, locality, and heterogeneity to perform scheduling dynamically and at fine granularity to avoid load imbalance. This fine-grain scheduler can use lightweight, flexible hardware support to keep overheads small as we scale up. Second, I will present a set of techniques that, together, enable scalable memory hierarchies that can be shared efficiently: ZCache, a cache design that achieves high associativity cheaply (e.g., 64-way associativity with the latency, energy and area of a 4-way cache) and is characterized by simple and accurate analytical models; Vantage, a cache partitioning technique that leverages the analytical guarantees of ZCache to implement scalable and efficient partitioning, enabling hundreds of threads to share the cache in a controlled manner, providing configurability and isolation; and SCD, which leverages ZCache to implement scalable cache coherence with QoS guarantees.

Biography

Daniel Sanchez is a PhD candidate in the Electrical Engineering Department at Stanford University. His research focuses on large-scale multicores, specifically on scalable and dynamic fine-grain runtimes and schedulers, hardware support for scheduling, scalable and efficient memory hierarchies, and architectures with QoS guarantees. He has earned an MS in Electrical Engineering from Stanford, and a BS in Telecommunication Engineering from the Technical University of Madrid (UPM).