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Monday, May 7 at 2:00pm
Computer Science Conference Room (HFH 1132)
I will review physics of the so-called "thermodynamic limit" on the energy consumption at computation, and C. Bennett's idea of reversible computing, which allows that limit to be avoided. Unfortunately, even if implemented in hardware virtually free of static power consumption (such as Parametric Quantron circuits), a genuinely reversible computation would require exponentially large resources. Selective reversibility sacrifices may sharply reduce this hardware overhead, but still leave the circuit speed and defect tolerance relatively low. The implementation of reversible computing in CMOS circuits, with their final static power consumption, adds additional challenges. I believe that the future of this concept will depend on the progress of IC patterning and 3D integration.
Konstantin K. Likharev received the Candidate (Ph.D.) degree from the Department of Physics of Lomonosov Moscow State University, Russia in 1969, and the habilitation degree of Doctor of Sciences from the Higher Attestation Committee of the U.S.S.R. in 1979. From 1969 to 1988 Dr. Likharev was a Member of Research Staff of Moscow State University, and from 1989 to 1991 the Head of the Laboratory of Cryoelectronics of that university. In 1991 he assumed a Professorship at Stony Brook University (Distinguished Professor since 2002). During his research career, Dr. Likharev worked in the fields of nonlinear classical and dissipative quantum dynamics, and solid-state physics and electronics, notably including superconductor electronics and nanoelectronics. He is an author of more than 250 original publications, 75 review papers and book chapters, 2 monographs, and several patents. Dr. Likharev is a Fellow of the APS and IEEE.
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Monday, February 27 at 10:00am
Engineering II, Room 1519 (map)
More than ten years ago, it was envisioned that the interconnects will be the limiters for continued increase in compute performance. Now we know that it's not the interconnects but power and energy that has been the limiter. As technology scaling continues providing abundance of transistors, and new architectures to continue to deliver performance in a given power envelope, we need to revisit the role of interconnects. This talk will touch on technology outlook, future architectures and design directions for continued performance towards Exascale, and the role of interconnects-whether they will help or hinder!
Shekhar Borkar graduated with an M.Sc in Physics from University of Bombay in 1979, MSEE from University of Notre Dame in 1981 and joined Intel Corp, where he worked on the 8051 family of microcontrollers, and Intel's supercomputers. His research interests are low power, high performance digital circuits, and high speed signaling. Shekhar is an Intel Fellow, an IEEE Fellow, and Director of Extreme-scale Technologies in Intel Labs.
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Monday, February 6 at 2:00p
Computer Science Conference Room (HFH 1132)
Life in the time of Dennard scaling was relatively easy for architects and the computer industry. Every process generation delivered twice as many transistors to a chip that could run at a 1.4 times faster clock rate and consume the same power as the previous generation. General purpose processors spent this bounty on deep pipelining for high clock rates, extreme out-of-order execution to mine instruction-level parallelism, and large on-chip caches. In today's post-Dennard scaling world that no longer benefits from voltage scaling, each generation of process technology doubles chip transistor count but requires 40% more power at the same clock rate as the previous generation. In this era, every computing device is energy or power limited and energy efficiency is equivalent to performance. This talk will describe the challenges facing computer architectures, ranging from mobile devices to high-performance computers. Using examples from contemporary architectures, it will then discuss strategies for creating energy-efficient computers, including extreme energy-efficient microarchitectures, parallelism, data locality, and specialization. The talk will conclude with a set of challenges for the architecture research community and discuss why this era is providing a renaissance of opportunity for innovative computer architectures.
Steve Keckler is the Director of Architecture Research at NVIDIA and Professor of both Computer Science and Electrical and Computer Engineering at the University of Texas at Austin. His research team at UT-Austin developed scalable parallel processor and memory system architectures, including non-uniform cache architectures; explicit data graph execution processors; and micro-interconnection networks to implement distributed processor protocols. At NVIDIA, Dr. Keckler focuses on parallel, energy-efficient architectures that span mobile through supercomputing platforms. He is a Fellow of the ACM, a Fellow of the IEEE, an Alfred P. Sloan Research Fellow, and a recipient of the ACM Grace Murray Hopper award, the President's Associates Teaching Excellence Award at UT-Austin, and the Edith and Peter O'Donnell award for Engineering. He earned a BS in Electrical Engineering from Stanford University and an MS and a Ph.D. in Computer Science from the Massachusetts Institute of Technology.